SN74LVC373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

SCAS295B - JANUARY 1993 - REVISED NOVEMBER 1994

features

• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages

EPIC is a trademark of Texas Instruments Incorporated.

description

This octal transparent D-type latch is designed for 2.7-V to 3.6-V V_CC operation.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74LVC373 is characterized for operation from -40°C to 85°C.

View more information about generic part numbers:SN74LVC373

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