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Data Sheet Abstract

SN74LVC138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

SCAS291B - MARCH 1993 - REVISED JULY 1995


features

description

This 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.

The SN74LVC138 is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight input lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

The SN74LVC138 is characterized for operation from -40°C to 85°C.


Title: 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
Product Family: MULTIPLEXERS
Device Functionality: DECODER/DEMULTIPLEXER
Orderable Devices: SN74LVC138D, SN74LVC138DBLE, SN74LVC138DR, SN74LVC138PWLE

View the complete PDF datasheet: scas291b.pdf (102 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LVC138

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