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Data Sheet Abstract

SN74ALVC16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS

SCAS276A - NOVEMBER 1993 - REVISED JULY 1995


features

description

This 18-bit (dual-octal) noninverting registered transceiver is designed for 2.7-V to 3.6-V VCC operation.

The SN74ALVC16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.

The SN74ALVC16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB\ or

CLKENBA\) inputs. It also provides parity-enable (SEL\) and parity-select (ODD/EVEN\) inputs and separate error-signal (ERRA\ or ERRB\) outputs for checking parity. The direction of data flow is controlled by OEAB\ and OEBA\. When SEL\ is low, the parity functions are enabled. When SEL\ is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVC16901 is available in TI's thin shrink small-outline (DGG) package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN74ALVC16901 is characterized for operation from -40°C to 85°C.


Title: 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS
Product Family: UNIVERSAL BUS TRANSCEIVERS (UBTS)
Device Functionality: BUS TRANSCEIVERS
Orderable Devices: SN74ALVC16901DGGR

View the complete PDF datasheet: scas276a.pdf (132 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ALVC16901

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