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Data Sheet Abstract

SN74ALVC16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SCAS263A - JANUARY 1993 - REVISED MARCH 1994


 

features

 

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description

This 18-bit universal bus transceiver is designed for 2.7-V to3.6-V VCC operation.

The SN74ALVC16600 combines D-type latches and D-type flip-flops toallow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA),and clock (and ) inputs. The clock can becontrolled by the clock-enable ( and ) inputs. ForA-to-B data flow, the device operates in the transparent mode whenLEAB is high. When LEAB is low, the A data is latched if is held at a high or low logiclevel. If LEAB is low, the A-bus data is stored in thelatch/flip-flop on the high-to-low transition of . Output enable is active low. When is low, the outputs are active.When is high, theoutputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses , LEBA, , and .

The SN74ALVC16600 is available in TI's shrink small-outline (DL)and thin shrink small-outline (DGG) packages, which provide twice theI/O pin count and functionality of standard small-outline packages inthe same printed-circuit-board area.

The SN74ALVC16600 is characterized for operation from -40°Cto 85°C.


Title: 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Product Family: UNIVERSAL BUS TRANSCEIVERS (UBTS)
Device Functionality: BUS TRANSCEIVERS
Orderable Devices: SN74ALVC16600DL, SN74ALVC16600DLR

View the complete PDF datasheet: scas263a.pdf (71 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ALVC16600

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