SCAS253B - MARCH 1990 - REVISED APRIL 1998
This 80-bit memory uses advanced low-power Schottky technology and features high speed and a fast fall-through time. It is organized as 16 words by 5 bits.
A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates up to 40 MHz in a bit-parallel format, word by word.
Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK) input. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect. When the memory is empty, UNCK signals have no effect.
Status of the FIFO memory is monitored by the FULL\, EMPTY\, FULL-1\, and EMPTY+1\ output flags. The FULL\ output is low when the memory is full and high when it is not full. The FULL-1\ output is low when the memory contains 15 data words. The EMPTY\ output is low when the memory is empty and high when it is not empty. The EMPTY+1\ output is low when one word remains in memory.
A low level on the reset (RST\) input resets the internal stack control pointers and also sets EMPTY\ low and sets FULL\, FULL-1\, and EMPTY+1\ high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LDCK, after either a RST\ pulse or from an empty condition, causes EMPTY\ to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the output flags. Cascading is easily accomplished in the word-width direction but is not possible in the word-depth direction.
The SN74ALS233B is characterized for operation from 0°C to 70°C.
View more information about generic part numbers:SN74ALS233B
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