54AC16652, 74AC16652 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SCAS242A - MARCH 1990 - REVISED APRIL 1996

Please be aware that an important notice concerningavailability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers theretoappears at the end of this data sheet.

features

Members of the Texas Instruments Widebus ^TM Family
Independent Registers and Enables for A and B Buses
Multiplexed Real-Time and Stored Data
Flow-Through Architecture Optimizes PCB Layout
Distributed V_CC and GND Pin Configurations Minimize High-Speed Switching Noise
EPIC ^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

EPIC and Widebus are trademarks of Texas Instruments

description

The 'AC16652 are 16-bit bus transceivers that consist of D-typeflip-flops and control circuitry arranged for multiplexedtransmission of data directly from the data bus or from the internalstorage registers. They can be used as two 8-bit transceivers or one16-bit transceiver.

Complementary output-enable (OEAB and ) inputs are provided to controlthe transceiver functions. Select-control (SAB and SBA) inputs areprovided to select whether real-time or stored data is transferred. Alow input level selects real-time data, and a high input levelselects stored data. The circuitry used for select control eliminatesthe typical decoding glitch that occurs in a multiplexer during thetransition between stored and real-time data. Figure 1 illustratesthe four fundamental bus-management functions that can be performedwith the 'AC16652.

Data on the A or B bus, or both, can be stored in the internal Dflip-flops by low-to-high transitions at the appropriate clock (CLKABor CLKBA) inputs regardless of the levels on the select-control oroutput-enable inputs. When SAB and SBA are in the real-time transfermode, it is also possible to store data without using the internalD-type flip-flops by simultaneously enabling OEAB and . In this configuration, eachoutput reinforces its input. Thus, when all other data sources to thetwo sets of bus lines are at high impedance, each set of bus linesremains at its last state.

The 74AC16652 is packaged in TI's shrink small-outline package(DL), which provides twice the I/O pin count and functionality ofstandard small-outline packages in the same printed-circuit-boardarea.

The 54AC16652 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The 74AC16652is characterized for operation from -40°C to 85°C.

The data-output functions may be enabled or disabled by avariety of level combinations at OEAB or . Data-input functions are alwaysenabled; i.e., data at the bus terminals is stored on everylow-to-high transition on the clock inputs.

Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered in order to load bothregisters.

Figure 1. Bus-Management Functions

Title: 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
Product Family: REGISTERED TRANSCEIVERS
Device Functionality: 16-BIT BUS TRANSCEIVER/REGISTER
Orderable Devices: 74AC16652DL, 74AC16652DLR

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View more information about generic part numbers:74AC16652

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