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Data Sheet Abstract

SN74ACT72211L, SN74ACT72221L, SN74ACT72231L,SN74ACT72241L 512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

 

SCAS222 - FEBRUARY 1993 - REVISED JUNE 1993


 

 

features

description

The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241Lare constructed with CMOS dual-port SRAM and are arranged as 512,1024, 2048, and 4096 9-bit words, respectively. Internal write andread address counters provide data throughput on a first-in,first-out (FIFO) basis. Full and empty flags prevent memory overflowand underflow, and two programmable flags (almost full and almostempty) are provided.

The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241Lare synchronous FIFOs, which means the data input port and dataoutput port each employ synchronous control. Write-enable (, WEN2/) signals allow the low-to-hightransition of the write clock (WCLK) to store data in memory, andread-enable (, ) signals allow the low-to-hightransition of the read clock (RCLK) to read data from memory. WCLKand RCLK are independent of one another and can operateasynchronously or be tied together for single-clock operation.

The empty-flag ()output is synchronized to RCLK and the full-flag () output is synchronized to WCLK toindicate absolute boundary conditions. Write operations areprohibited when is low, andread operations are prohibited when is low. Two programmable flags, programmable almostempty () andprogrammable almost full (),can both be programmed to indicate any measure of memory fill. Afterreset, defaults toempty+7 and defaults tofull-7. Flag-offset programming control is similar to a memory writewith the use of the load (WEN2/) signal.

These devices are suited for providing a data channel between twobuses operating at asynchronous or synchronous rates. Applicationsinclude use as rate buffers for graphics systems and high-speedqueues for communication systems. A 9-bit-wide data path is providedfor the transmission of byte data plus a parity bit or packet-framinginformation.

The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241Lare characterized for operation from 0°C to 70°C.


Title: 512 X 9, 1024 X 9, 2048 X9, AND 4096 X 9 SYNCHRONOUS FIFO MEMORIES
Product Family: SYNCHRONOUS FIFOS
Device Functionality: 4K X 9
Orderable Devices: SN74ACT72211L15RJ, SN74ACT72211L20RJ, SN74ACT72211L20RJR, SN74ACT72211L25RJ, SN74ACT72211L35RJ, SN74ACT72211L50RJ, SN74ACT72211L50RJR, SN74ACT72211L15RJ, SN74ACT72211L20RJ, SN74ACT72211L20RJR, SN74ACT72211L25RJ, SN74ACT72211L35RJ, SN74ACT72211L50RJ, SN74ACT72211L50RJR, SN74ACT72221L15RJ, SN74ACT72221L20RJ, SN74ACT72221L25RJ, SN74ACT72221L35RJ, SN74ACT72221L50RJ, SN74ACT72221L15RJ, SN74ACT72221L20RJ, SN74ACT72221L25RJ, SN74ACT72221L35RJ, SN74ACT72221L50RJ, SN74ACT72231L15RJ, SN74ACT72231L20RJ, SN74ACT72231L20RJR, SN74ACT72231L25RJ, SN74ACT72231L35RJ, SN74ACT72231L50RJ, SN74ACT72231L15RJ, SN74ACT72231L20RJ, SN74ACT72231L20RJR, SN74ACT72231L25RJ, SN74ACT72231L35RJ, SN74ACT72231L50RJ, SN74ACT72241L15RJ, SN74ACT72241L20RJ, SN74ACT72241L20RJR, SN74ACT72241L25RJ, SN74ACT72241L35RJ, SN74ACT72241L50RJ, SN74ACT72241L15RJ, SN74ACT72241L20RJ, SN74ACT72241L20RJR, SN74ACT72241L25RJ, SN74ACT72241L35RJ, SN74ACT72241L50RJ

View the complete PDF datasheet: scas222.pdf (297 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ACT72211L, SN74ACT72211L15, SN74ACT72211L20, SN74ACT72211L25, SN74ACT72211L35, SN74ACT72211L50, SN74ACT72221L, SN74ACT72221L15, SN74ACT72221L20, SN74ACT72221L25, SN74ACT72221L35, SN74ACT72221L50, SN74ACT72231L, SN74ACT72231L15, SN74ACT72231L20, SN74ACT72231L25, SN74ACT72231L35, SN74ACT72231L50, SN74ACT72241L, SN74ACT72241L15, SN74ACT72241L20, SN74ACT72241L25, SN74ACT72241L35, SN74ACT72241L50

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