SN74ACT8994 DIGITAL BUS MONITOR IEEE STD 1149.1 (JTAG) SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER

SCAS196E - JULY 1990 - REVISED DECEMBER 1996

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features

• Member of the Texas Instruments SCOPE^TM Family of Testability Products
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• Contains a 1024-Word by 16-Bit Random-Access Memory (RAM) to Store the States of a Digital Bus
• Test Operations Are Synchronous to the Test Clock or System Clock(s)
• Contains Texas Instruments Event Qualification Module for Real-Time System Test
• Eight Protocols for On-Line Signal Monitoring and Test Operations
• Inputs Are TTL-Voltage Compatible
• Performs Parallel-Signature Analysis (PSA) of Data Inputs With User-Definable Feedback
• Data Inputs Are Maskable During PSA Operations
• Cascaded PSA Mode Allows Compression of Parallel Data Paths Greater Than 16 Bits in Width
• Direct Memory Access (DMA) Speeds Memory and Register File Read/Write Operations
• Power-Down Mode When RAM Is Idling Reduces Power Dissipation
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• Packaged in 28-Pin Plastic Chip Carriers

  SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

   

description

The SN74ACT8994 digital bus monitor (DBM) is a member of the TexasInstruments SCOPE^TM testability integrated-circuit family.This family of components supports IEEE Standard 1149.1-1990 (JTAG)boundary scan to facilitate testing of complex circuit-boardassemblies. The DBM is a boundary-scannable device designed tomonitor and/or store the values of a digital bus up to 16 bits inwidth. It resides in parallel with the bus being monitored.

Data at the D-input pins can be stored in a scannablerandom-access memory (RAM). Up to 1024 words of 16 bits can bestored. A parallel-signature analysis (PSA) can be performed on thedata or on the contents of memory. The PSA operations use alinear-feedback shift-register technique to compress data into asignature. The user can configure the device to mask any combinationof data inputs and control the feedback used during PSA operations.

The DBM receives instructions via the IEEE Standard 1149.1-1990test access port (TAP) interface. The TAP interface consists of testclock (TCK), test mode select (TMS), test data input (TDI), and testdata output (TDO) pins.

The DBM can be operated in the off-line mode or the on-line mode.In the off-line mode, the device performs test operations independentof system conditions. Off-line test operations includeparallel-signature analysis (PSA) on the contents of RAM and externaltest.

In the on-line mode, the DBM can be configured to perform testoperations that are initiated based on system conditions and thatoperate synchronously to a logical combination of one or more systemclocks. The device allows sample, storage, and/or PSA operations tobe performed according to one of eight protocols. Compare patterns,which can be stored in the event-qualification module (EQM), allowthe user to define specific values of the 16-bit bus for which thetest operations are to be performed.

The 1024-word by 16-bit RAM and the EQM register files can beserially accessed using IEEE-Standard-1149.1-1990-compatible read andwrite instructions. However, direct memory access (DMA) instructionsalso are provided to speed transfer of large amounts of data to andfrom the RAM and EQM.

The polynomial input/output (PIO) is a bidirectional pin used tocascade more than one DBM to provide signature analysis on a buslarger than 16 bits.

The SN74ACT8994 is characterized for operation from 0°C to70°C.

View more information about generic part numbers:SN74ACT8994

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