SN74ACT7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS191C - MARCH 1991 - REVISED APRIL 1998

features

Member of the Texas Instruments Widebus^TM Family
Free-Running Read and Write Clocks Can Be Asynchronous or Coincident
Read and Write Operations Synchronized to Independent System Clocks
Input-Ready Flag Synchronized to Write Clock
Output-Ready Flag Synchronized to Read Clock
512 Words by 18 Bits
Low-Power Advanced CMOS Technology
Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag
Bidirectional Configuration and Width Expansion Without Additional Logic
Fast Access Times of 12 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
Data Rates up to 67 MHz
Pin-to-Pin Compatible With SN74ACT7805 and SN74ACT7813
Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing
Widebus and OEC are trademarks of Texas Instruments Incorporated.

description

The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed V_CC and GND pins, along with Texas Instruments patented output edge control (OEC^TM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

The SN74ACT7803 is characterized for operation from 0°C to 70°C.

Title: 512 X 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
Product Family: CLOCKED FIFOS
Device Functionality: 512 X 18
Orderable Devices: SN74ACT7803-15DL, SN74ACT7803-15DLR, SN74ACT7803-20DL, SN74ACT7803-20DLR, SN74ACT7803-25DL, SN74ACT7803-25DLR, SN74ACT7803-40DL, SN74ACT7803-40DLR, SN74ACT7803-15DL, SN74ACT7803-15DLR, SN74ACT7803-20DL, SN74ACT7803-20DLR, SN74ACT7803-25DL, SN74ACT7803-25DLR, SN74ACT7803-40DL, SN74ACT7803-40DLR

View the complete PDF datasheet: scas191c.pdf (191 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ACT7803, SN74ACT7803-15, SN74ACT7803-20, SN74ACT7803-25, SN74ACT7803-40

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