SCAS190E - JUNE 1990 - REVISED JANUARY 1997
Please be aware that an important notice concerningavailability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers theretoappears at the end of this data sheet.
m Process SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
The 'ACT8990 test-bus controllers (TBC) are members of the TexasInstruments SCOPETM testability integrated-circuit family.This family of components supports IEEE Standard 1149.1-1990 (JTAG)boundary scan to facilitate testing of complex circuit-boardassemblies. The 'ACT8990 differ from other SCOPETMintegrated circuits. Their function is to control the JTAGserial-test bus rather than being target boundary-scannable devices.
The required signals of the JTAG serial-test bus - test clock(TCK), test mode select (TMS), test data input (TDI), and test dataoutput (TDO) can be connected from the TBC to a target device withoutadditional logic. This is done as a chain of IEEE Standard1149.1-1990 boundary-scannable components that share the sameserial-test bus. The TBC generates TMS and TDI signals for itstarget(s), receives TDO signals from its target(s), and buffers itstest clock input (TCKI) to a test clock output (TCKO) fordistribution to its target(s). The TMS, TDI, and TDO signals can beconnected to a target directly or via a pipeline, with a retimingdelay of up to 31 bits. Since the TBC can be configured to generateup to six separate TMS signals [TMS (5-0)], it can be used to controlup to six target scan paths that are connected in parallel (i.e.,sharing common TCK, TDI, and TDO signals).
While most operations of the TBC are synchronous to TCKI, atest-off (TOFF\) input is provided for output control of the targetinterface, and a test-reset (TRST\) input is provided forhardware/software reset of the TBC. In addition, four event [EVENT(3-0)] I/Os are provided for asynchronous communication to targetdevice(s). Each event has its own event generation/detection logic,and detected events can be counted by two 16-bit counters.
The TBC operates under the control of a hostmicroprocessor/microcontroller via the 5-bit address bus [ADRS (4-0)]and the 16-bit read/write data bus [DATA (15-0)]. Read (RD\) andwrite (WR\) strobes are implemented such that the criticalhost-interface timing is independent of the TCKI period. Any one of24 registers can be addressed for read and/or write operations. Inaddition to control and status registers, the TBC contains twocommand registers, a read buffer, and a write buffer. Status of theTBC is transmitted to the host via ready (RDY\) and interrupt (INT\)outputs.
Major commands can be issued by the host to cause the TBC togenerate the TMS sequences necessary to move the target(s) from anystable test-access-port (TAP) controller state to any other stableTAP state, to execute instructions in the Run-Test/Idle TAP state, orto scan instruction or test data through the target(s). A 32-bitcounter can be preset to allow a predetermined number of execution orscan operations.
Serial data that appears at the selected TDI input (TDI1 or TDI0)is transferred into the read buffer, which can be read by the host toobtain up to 16 bits of the serial-data stream. Serial data that istransmitted from the TDO output is written by the host to the writebuffer.
The SN54ACT8990 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ACT8990 is characterized for operation from 0°C to70°C.
NC - No internal connection
View more information about generic part numbers:SN54ACT8990, SN74ACT8990
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.