



SCAS166A - JUNE 1990 - REVISED APRIL 1996
EPIC and Widebus are trademarks of Texas Instrumentsdescription
The 'ACT16833 consist of two noninverting 8-bit to 9-bit paritybus transceivers and are designed for communication between databuses. For each transceiver, when data is transmitted from the A busto the B bus, an odd-parity bit is generated and output on the parityI/O pin (1PARITY or 2PARITY). When data is transmitted from the B busto the A bus, 1PARITY or 2PARITY is configured as an input andcombined with the B-input data to generate an active-low error flagif odd parity is not detected.
The error (1
or 2
or 2
on the low-to-high transition of the clock (1CLK or2CLK) input. 1
or 2
or 2
The output-enable (
and
are low, data is transferred from the A bus to the Bbus and inverted parity is generated. Inverted parity is a forcederror condition that gives the designer more system diagnosticcapability.
The 74ACT16833 is packaged in TI's shrink small-outline package,which provides twice the I/O pin count and functionality of standardsmall-outline packages in the same printed-circuit-board area.
The 54ACT16833 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The74ACT16833 is characterized for operation from -40°C to85°C.
View more information about generic part numbers:74ACT16833
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.



