54ACT16657, 74ACT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

SCAS164A - JANUARY 1991 - REVISED APRIL 1996

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features

Members of the Texas Instruments Widebus^TM Family
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes PCB Layout
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

EPIC and Widebus are trademarks of Texas Instruments

description

The 'ACT16657 contain two noninverting octal transceiver sectionswith separate parity generator/checker circuits and control signals.For either section, the transmit/receive (1T/R\ or 2T/R\) inputdetermines the direction of data flow. When 1T/R\ (or 2T/R\) is high,data flows from the 1A (or 2A) port to the 1B (or 2B) port (transmitmode); when 1T/R\ (or 2T/R\) is low, data flows from the 1B (or 2B)port to the 1A (or 2A) port (receive mode). When the output-enable(1 or 2) input is high, both the 1A (or2A) and 1B (or 2B) ports are in the high-impedance state.

Odd or even parity is selected by a logic high or low level,respectively, on the 1ODD/ (or2ODD/) input.1PARITY (or 2PARITY) carries the parity bit value; it is an outputfrom the parity generator/checker in the transmit mode and an inputto the parity generator/checker in the receive mode.

In the transmit mode, after the 1A (or 2A) bus is polled todetermine the number of high bits, 1PARITY (or 2PARITY) is set to thelogic level that maintains the parity sense selected by the level atthe 1ODD/ (or 2ODD/) input. For example, if 1ODD/ is low (even parity selected) andthere are five high bits on the 1A bus, then 1PARITY is set to thelogic high level so that an even number of the nine total bits (eight1A-bus bits plus parity bit) are high.

In the receive mode, after the 1B (or 2B) bus is polled todetermine the number of high bits, the 1 (or 2) output logic level indicateswhether or not the data to be received exhibits the correct paritysense. For example, if 1ODD/ ishigh (odd parity selected), 1PARITY is high, and there are three highbits on the 1B bus, then 1 islow, indicating a parity error.

The 74ACT16657 is packaged in TI's shrink small-outline package,which provides twice the I/O pin count and functionality of standardsmall-outline packages in the same printed-circuit-board area.

The 54ACT16657 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The74ACT16657 is characterized for operation from -40°C to85°C.

Title: 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
Product Family: PARITY TRANSCEIVERS
Device Functionality: 16-BIT TRANSCEIVER
Orderable Devices: 74ACT16657DL, 74ACT16657DLR

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View more information about generic part numbers:74ACT16657

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