SCAS134 - D3445, MARCH 1990 - REVISED APRIL 1993
m Process
These devices consist of bus transceiver circuits, D-typeflip-flops, and control circuitry arranged for multiplexedtransmission of data directly from the data bus or from the internalstorage registers. Enables GAB and G\BA are provided to control thetransceiver functions. SAB and SBA control pins are provided toselect whether real-time or stored data is transferred. The circuitryused for select control eliminates the typical decoding glitch thatoccurs in a multiplexer during the transition between stored andreal-time data.
A low input level selects real-time data and a high selects storeddata. Figure 1 illustrates the four fundamental bus-managementfunctions that can be performed with the octal bus transceivers andregisters. Data on the A or B bus, or both, can be stored in theinternal D flip-flops by low-to-high transitions at the appropriateclock pins (CAB or CBA) regardless of the select or enable controlpins. When SAB and SBA are in the real-time transfer mode, it is alsopossible to store data without using the internal D-type flip-flopsby simultaneously enabling GAB and G\BA. In this configuration, eachoutput reinforces its input. Thus, when all other data sources to thetwo sets of bus lines are at high impedance, each set of bus linesremains at its last state.
The 74ACT11651 is characterized for operation from - 40°C to85°C.
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