Data Sheet Abstract: CDC208, CDC208-7:DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS

DUAL 1-LINE TO 4-LINE CLOCK DRIVERSWITH 3-STATE OUTPUTS

SCAS109E - APRIL 1990 - REVISED MAY 1997

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features

Low-Skew Propagation Delay Specifications for Clock-Driver Applications
TTL-Compatible Inputs and CMOS-Compatible Outputs
Flow-Through Architecture Optimizes PCB Layout
Center-Pin V_CC and GND Pin Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-um Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages and Standard Plastic 300-mil DIPs (N)

description

The CDC208/208-7 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

The CDC208/208-7 is characterized for operation from -40°C to 85°C.

Title: DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS
Product Family: OTHER DIGITAL LOGIC
Device Functionality: BUFFER
Orderable Devices: CDC208DBLE, CDC208DW, CDC208DWR, CDC208N, CDC208-7DW, CDC208-7DWR

View the complete PDF datasheet: scas109e.pdf (163 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:CDC208, CDC208-7

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