CDC209, CDC209-7 DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS

SCAS108D - MARCH 1990 - REVISED MAY 1997

features

CDC209 Replaces 74AC11208
CDC209-7 Replaces 74AC11208-7
Low-Skew Propagation Delay Specifications for Clock-Driver Applications
CMOS-Compatible Inputs and Outputs
Flow-Through Architecture Optimizes PCB Layout
Characterized for Operation at 5-V and 3.3-V V_CC
Center-Pin V_CC and GND Pin Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-um Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline Package (DW) and Standard Plastic 300-mil DIPs (N)
EPIC is a trademark of Texas Instruments Incorporated.

description

The CDC209/209-7 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

The CDC209/209-7 is characterized for operation fromT_A = -40°C to 85°C.

Title: DUAL 1-LINE TO 4-LINE CLOCK DRIVERS WITH 3-STATE OUTPUTS
Product Family: OTHER DIGITAL LOGIC
Device Functionality: BUFFER
Orderable Devices: CDC209DBLE, CDC209DW, CDC209DWR, CDC209N, CDC209-7DW, CDC209-7DWR

View the complete PDF datasheet: scas108d.pdf (161 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:CDC209, CDC209-7

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.