54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

SCAS073A - JUNE 1989 - REVISED APRIL 1993

features

Flow-Through Architecture Optimizes PCB Layout
Center-Pin V_CC and GND Configuration Minimizes High-Speed Switching Noise
EPIC ^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015
Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

EPIC is a trademark of Texas Instruments

description

These devices contain two independent J-K negative-edge-triggeredflip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of theother inputs. When preset and clear are inactive (high), data at theJ and K inputs meeting the setup time requirements are transferred tothe outputs on the negative-going edge of the clock pulse. Clocktriggering occurs at a voltage level and is not directly related tothe fall time of the clock pulse. Following the hold time interval,data at the J and K inputs may be changed without affecting thelevels at the outputs. These versatile flip-flops can perform astoggle flip-flops by tying J and K high.

The 54AC11112 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The 74AC11112is characterized for operation from -40°C to 85°C.

Title: DUAL J-K NEGATIVE-EDGE-TRIG FLIP-FLOPS W/CLEAR & PRESET
Product Family: OTHER FLIP-FLOPS
Device Functionality: DUAL J-K FLIP-FLOP
Orderable Devices: 74AC11112D, 74AC11112DR, 74AC11112N

View the complete PDF datasheet: scas073a.pdf (87 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:74AC11112

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