74AC11239 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

SCAS072A - JULY 1989 - REVISED APRIL 1993

features

Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception
Flow-Through Architecture to Optimize PCB Layout
Center-Pin V_CC and GND Configurations to Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small Outline Packages, and Standard Plastic 300-mil DIPs
EPIC is a trademark of Texas Instruments Incorporated.

description

The 74AC11239 circuit is designed to be used in high-performancememory-decoding or data- routing applications requiring very shortpropagation delay times. In high-performance memory systems, thisdecoder can be used to minimize the effects of system decoding. Whenemployed with high-speed memories utilizing a fast enable circuit,the delay times of this decoder and the enable time of the memory areusually less than the typical access time of the memory. This meansthat the effective system delay introduced by the decoder isnegligible.

The 74AC11239 is comprised of two individual two-line to four-linedecoders in a single package. The active-low enable input can be usedas a data line in demultiplexing applications. Thesedecoders/demultiplexers feature fully buffered inputs, each of whichrepresents only one normalized load to its driving circuit.

The 74AC11239 is characterized for operation from - 40°C to85°C.

Title: DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER
Product Family: DEMULTIPLEXERS
Device Functionality: DECODER/DEMULTIPLEXER
Orderable Devices: 74AC11239D, 74AC11239N

View the complete PDF datasheet: scas072a.pdf (91 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:74AC11239

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