74AC11139 DUAL 2-LINE DECODER/DEMULTIPLEXER

SCAS070B - JULY 1989 - REVISED APRIL 1996

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features

Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception
Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)

EPIC is a trademark of Texas Instruments

description

The 74AC11139 circuit is designed to be used in high-performancememory-decoding or data-routing applications requiring very shortpropagation delay times. In high-performance memory systems, thisdecoder can be used to minimize the effects of system decoding. Whenemployed with high-speed memories utilizing a fast enable circuit,the delay times of this decoder and the enable time of the memory areusually less than the typical access time of the memory. This meansthat the effective system delay introduced by the decoder isnegligible.

The 74AC11139 is composed of two individual 2-line to 4-linedecoders in a single package. The active-low enable input can be usedas a data line in demultiplexing applications. Thisdecoder/demultiplexer features fully buffered inputs, each of whichrepresents only one normalized load to its driving circuit.

The 74AC11139 is characterized for operation from -40°C to85°C.

Title: DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER
Product Family: DEMULTIPLEXERS
Device Functionality: DECODER/DEMULTIPLEXER
Orderable Devices: 74AC11139D, 74AC11139DR, 74AC11139N, 74AC11139PWLE

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View more information about generic part numbers:74AC11139

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