74ACT11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET

SCAS064A - D3339, JUNE 1989 - REVISED APRIL 1993

features

Inputs Are TTL-Voltage Compatible
Fully Buffered to Offer Maximum Isolation From External Disturbance
Flow-Through Architecture Optimizes PCB Layout
Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

EPIC is a trademark of Texas Instruments

description

This device contains two independent J-K negative-edge-triggeredflip-flops. A low level at the or input sets orresets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the Jand K inputs meeting the setup time requirements are transferred tothe outputs on the negative-going edge of the clock pulse. Clocktriggering occurs at a voltage level and is not directly related tothe fall time of the clock pulse. Following the hold-time interval,data at the J and K inputs may be changed without affecting thelevels at the outputs. These versatile flip-flops can perform astoggle flip-flops by tying J and K high.

The 74ACT11112 is characterized for operation from - 40°C to85°C.

Title: DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET
Product Family: OTHER FLIP-FLOPS
Device Functionality: DUAL J-K FLIP-FLOP
Orderable Devices: 74ACT11112D, 74ACT11112DR, 74ACT11112N

View the complete PDF datasheet: scas064a.pdf (69 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:74ACT11112

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