SCAS061A - D2957, JULY 1987 - REVISED APRIL 1993
m Process
EPIC is a trademark of Texas Instrumentsdescription
These devices consist of bus transceiver circuits, 3-stateoutputs, D-type flip-flops, and control circuitry arranged formultiplexed transmission of data directly from the data bus or fromthe internal storage registers. Data on the A or B bus will beclocked into the registers on the low-to-high transition of theappropriate clock pin (CAB or CBA). Figure 1 illustrates the fourfundamental bus-management functions that can be performed with theoctal bus transceivers and registers.
Enable (G\) and direction (DIR) pins are provided to control thetransceiver functions. In the transceiver mode, data present at thehigh-impedance port may be stored in either register or in both. Theselect controls (SAB and SBA) can multiplex stored and real-time(transparent mode) data. The circuitry used for select control willeliminate the typical decoding glitch which occurs in a multiplexerduring the transition between stored and real-time data. Thedirection control determines which bus will receive data when enableG\ is active (low). In the isolation mode (control G\ high), A datamay be stored in one register and/or B data may be stored in theother register.
When an output function is disabled, the input function is stillenabled and may be used to store and transmit data. Only one of thetwo buses, A or B, may be driven at a time.
The 74ACT11646 is characterized for operation from - 40°C to85°C.
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