74AC11623 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SCAS058A - JULY 1987 - REVISED APRIL 1993

features

Local Bus-Latch Capability
Flow-Through Architecture Optimizes PCB Layout
Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline Packages, and Standard Plastic 300-mil DIPs

EPIC is a trademark of Texas Instruments

description

These octal bus transceivers are designed for asynchronouscommunication between data buses. The control function implementationallows for maximum flexibility in timing.

These devices transmit data from the A bus to the B bus or fromthe B bus to the A bus depending upon the level at the output-enable(OEAB or ) inputs. Theoutput-enable inputs can be used to disable the device so that thebuses are effectively isolated.

The dual-enable configuration gives these devices the capabilityto store data by simultaneous enabling of OEAB and . Each output reinforces its inputin this transceiver configuration. Thus, when both control inputs areenabled and all other data sources to the two sets of bus lines areat high impedance, both sets of bus lines (16 in all) will remain attheir last states. The 8-bit codes appearing on the two sets of buseswill be complementary for the 74AC11623.

The 74AC11623 is characterized for operation from -40°C to85°C.

Title: OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Product Family: UNIVERSAL BUS TRANSCEIVERS (UBTS)
Device Functionality: OCTAL BUS TRANSCEIVER
Orderable Devices: 74AC11623DW, 74AC11623NT

View the complete PDF datasheet: scas058a.pdf (88 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:74AC11623

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