74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

SCAS042B - MAY 1988 - REVISED APRIL 1996

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features

Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception
Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)

EPIC is a trademark of Texas Instruments

description

The 74AC11138 circuit is designed to be used in high-performancememory-decoding or data-routing applications requiring very shortpropagation delay times. In high-performance memory systems, thisdecoder can be used to minimize the effects of system decoding. Whenemployed with high-speed memories utilizing a fast enable circuit,the delay times of this decoder and the enable time of the memory areusually less than the typical access time of the memory. This meansthat the effective system delay introduced by the decoder isnegligible.

The conditions at the binary-select (A, B, C) inputs and the threeenable (G1, , ) inputs select one of eight outputlines. Two active-low and one active-high enable inputs reduce theneed for external gates or inverters when expanding. A 24-linedecoder can be implemented without external inverters and a 32-linedecoder requires only one inverter. An enable input can be used as adata input for demultiplexing applications.

The 74AC11138 is characterized for operation from -40°C to85°C.

Title: 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
Product Family: DEMULTIPLEXERS
Device Functionality: DECODER/DEMULTIPLEXER
Orderable Devices: 74AC11138D, 74AC11138DR, 74AC11138N, 74AC11138PWLE

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View more information about generic part numbers:74AC11138

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