FIFO MEMORIES: SOLUTIONS FOR INCREASING CLOCK RATES AND DATA WIDTHS

Four TI CMOS clocked first-in first-out (FIFO) memories the 2k´9 SN74ACT807, the 512´18 SN74ACT7803, the 256´18 SN74ACT7805, and the 64´18 SN748ACT7813 provide synchronous interfaces that conform to the requirements of many high-performance systems. The FIFO architecture limits the glue logic necessary and limits the timing constraints to the system. Each FIFO is easily expanded to accommodate varying word widths. The SN74ACT7803/05/13 can be arranged to form a bidirectional FIFO. This document describes the clocked FIFOs, their flag synchronization and their compact packaging.

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