



SYSTEM LAYOUT GUIDELINES TNETE2101 10/100 MBITS/S ETHERNET PHYSICAL LAYER DEVICThe goal of these guidelines is to provide hardware systems designers with the information and recommendations needed for achieving the highest level of cost-effective system performance when using the Texas Instruments (TI(TM)) TNETE2101 10/100 Mbps ethernet physical layer interface (PHY) device in their networking applications.
Careful planning and special considerations are required during the schematic and layout stages of high-speed system design in order to create an operating environment which is not only stable and robust, but also emits a minimal amount of radiated energy (i.e., low EMI).
View the complete PDF document: spwa012.pdf (70 K Bytes) (Requires Acrobat Reader 3.x) Go to the Engineering Design Center to locate information on other TI Semiconductor devices.
![]() ![]() ![]() ![]() (c) Copyright 1998 Texas Instruments Incorporated. All rights reserved. Trademarks, Important Notice! |