TMS320C6201/6701 DSP HOST PORT INTERFACE (HPI)PERFORMANCE

This document describes how to determine the number of CPU cycles required to transfer data between the host CPU and the Texas Instruments (TIä) TMS320C6201/6701 digital signal processor (DSP) using the Host Port Interface (HPI).

The host has direct access to the processor's data memory via the 16-bit HPI. The number of cycles required for a data transfer between the host CPU and the TMS320C6201/6701 depends on the transfer type (read and write, with and without auto-increment, and internal and external memory type).

This document provides equations to calculate the time required to read and write a data word to the TMS320C6201/6701 DSP memory. Timing diagrams are included to illustrate signal relationships for memory reads and writes.

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