IMPLEMENTING V.32BIS VITERBI DECODING ON THE TMS320C62XX DSP

This paper describes the implementation of the V.32bis decoding

algorithm on the Texas Instruments (TIä) TMS320C62xx digital signal

processor (DSP). The V.32bis Viterbi decoder algorithm is based on a

soft-decision maximum-likelihood decoding technique. (Details on the

theory behind this algorithm are described in the TI publication, DSP

Solutions for Telephony and Data/Facsimile Modems, literature number

SPRA073.)

This V.32bis decoding algorithm is written using hand-coded assembly

and is C callable. Implementation is divided into seven steps as

follows:

Step 1. Opening the Function

Step 2. Euclidean Distance Calculation

Step 3. Find Shortest Distances

Step 4. Calculate Accumulate Distances

Step 5. Trace Backward for Path-State

Step 6. Differentiate

Step 7. Closing the Function

Appendix A contains the C code implementation of the V.32bis Viterbi

algorithm. Appendix B contains the C62xx assembly code implementation.

Appendix C contains the main C program to test the performance of the

Viterbi code.

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