DEMONSTRATING TMS320C2XX PIPELINE OPERATION DURING AN INTERRUPT

This application brief describes the behavior of the Texas Instruments (TI(TM)) TMS320C2xx pipeline during an interrupt occurring around the SETC and CLRC instructions. This brief also explains how to change the appropriate bit in the IMR register to protect a block of code without globally disabling interrupts.

Each scenario was tested using the TMS320C209SE ('C209SE) DSP and its internal timer as the interrupt source. Pipeline operation was verified using actual code traces on the XDS511/522 emulator.

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