PARALLELIZATION OF A H.263 ENCODER FOR THE TMS320C80 MVP

The coding of digital video sequences has been paid increasing attention over the past few years. Algorithms and standards such as MPEG1, MPEG2 or H.261 have been developed allowing more and more compression. A new standard in this field is H.263 which has been recently adopted by the ITU. It is intended for videoconferencing, videophoning, surveillance and other low bit rate applications (below 28,8 kbit/s). Compared to its predecessor H.261 it has additional modes and improved motion estimation resulting in an improved coding efficiency and allowing to transmit video sequences over analog telephone lines. H.263 is computational intensive and needs a powerful hardware for its implementation.

This paper describes a real-time implementation of a H.263 encoder on a Texas Instruments(TI(TM)) TMS320C80 (MVP) multiprocessor system. In order to exploit the four DSPs and the RISC processor of the MVP the encoding algorithm must be parallelized. The paper discusses the main issues of parallelization for the MVP: Load balance and appropriate scheduling taking into account the bandwidth of the memory interface and the size of internal memory. For real-time applications of video coders there is another important criterion: Minimal coding delay.

This document was part of the first European DSP Education and Research Conference that took place September 26 and 27, 1996 in Paris. For information on how TI encourages students from around the world to find innovative ways to use DSPs, see TI's World Wide Web site at www.ti.com.

*DISCLAIMER: This document was part of the DSP Solution Challenge 1995 European Team Papers. It may have been written by someone whose native language is not English. TI assumes no liability for the quality of writing and/or the accuracy of the information contained herein.

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