PARALLELIZING AND OPTIMIZING A SIMULATOR KERNEL ON A MULTI-DSP ARCHITECTURE.

This application report describes the parallelization and optimization of a hydraulic simulator kernel on a Texas Instruments (TI™) TMS320C40 multi-DSP (digital signal processor) platform. Research is based on A. Riel's diploma thesis. This report includes references to works directly connected with this thesis.

Three different parallel versions of the initially sequential simulator are implemented and optimized for various hardware and software-related issues. The paradigms applied for parallelization are discussed along with the effects certain optimizations have on simulator performance.

The various parallelization and optimization approaches for real-time implementation are judged by measuring the comparable speedup and simulation times for all parallel versions of the same simulator. This application report includes selected interpreted data of this research.

This document was an entry in TI's DSP Solutions Challenge, an annual contest organized by TI to encourage students from around the world to find innovative ways to use DSPs. For more information on the TI DSP Solutions Challenge, see TI's World Wide Web site at www.ti.com.

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*DISCLAIMER: This document was part of the DSP Solution Challenge 1995 European Team Papers. It may have been written by someone whose native language is not English. TI assumes no liability for the quality of writing and/or the accuracy of the information contained herein.

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