PARITY GENERATION ON THE TMS320C54X

In many applications, simple parity checks are often introduced to provide some minimal error detection capabilities when the transmission channels are less than perfect. The 8-bit data bus in personal computers is protected with the addition of a ninth parity bit. Serial asynchronous data communications frequently embed an extra parity bit in the data which is to be transmitted. Several of the digital cellular phones utilize simple parity checks to protect data transmission over a less than robust channel. Although it is far from an optimal means of ensuring transmission errors are detected, parity tends to be fairly simple to implement in either hardware or software, and introduces minimal overhead in the transmitted message.

This document discusses how the designer can use the TMS320C54x DSPs to generate parity to ensure data transmission has not been corrupted. It cintains several block diagrams illustrating the process, and code listings needed to implement the process.

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