REDUCING SYSTEM POWER REQUIREMENTS

With the ever-growing need for battery-operated systems, the need for low-power designs has increased significantly in recent years. These low-power applications have expanded to include high-speed DSP designs. It is necessary to design with high-speed devices while maintaining an overall power reduction. This document discusses a number of ways to reduce your system power, ranging from the use of CMOS logic to varying the clock rates of the logic to powering down unused logic. Graphs are given, showing the resultant power savings.

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