DOUBLELENGTH FLOATING-POINT ARITHMETIC ON THE TMS320C30 (CONTAINS SCANNED TEXT)

This chapter, reprinted from "IEEE Micro Magazine", describes the third generation of the TMS320 family of digital signal processors, the TMS320C30. It describes the origin and development of the 32-bit floating-point device. The topics covered include:

- An overview of the characteristics of the TMS320C30 processor

- A description of the architecture of the 320C30

- A description of the software features of the programmable DSP

- A description of development tools and support

- The types of demanding applications for which the 320C30 is most suitable

Support graphics include:

- Architecture block diagrams

- Diagrams showing on-chip memory, cache and buses, the 320C30 central processing unit, and peripheral bus and peripherals

- A pipeline of 320C30 instructions

- Sample code implementations

The chapter closes with an endnote about the likely direction of this technology, a list of references and some biographical information about the authors.

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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