PARALLEL 1-D FFT IMPLEMENTATION WITH TMS320C4X DSPS

This document discusses the theory of one-dimensional fast Fourier transforms (1-D FFT), parallel 1-D FFT, and parallel decimation in frequency (DIF) FFT algorithms. Two schemes are presented for the parallel DIF FFT algorithm along with a discussion of partitioned 1-D FFT. An implementation of 1-D FFT using the TMS320C40 parallel processing development system (PPDS) is shown. The TMS320C40 is a 32-bit floating-point parallel digital signal processor (DSP). The appendices illustrate regular serial DIF and decimation in time (DIT) implementations providing comparative measures for the parallel programs.

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