HIGH SPEED CLOCK DISTRIBUTION DESIGN TECHNIQUES FOR CDC 2509/2510/509/516

The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loop (PLL) technology.

To meet the designer's need for high-performance clock system components, Texas Instruments has developed PLL Clock Drivers that push the clock speeds up to 125 MHz. The focus of this application note will be on Clock Distribution chips specifically designed for use with Synchronous DRAMs. The clock driver series designed for buffered SDRAM applications includes CDC509, CDC516, CDC2509, CDC2510 and CDC2516. Some of the advanced features offered by these chips include:

Phase-Lock Loop Clock Distribution for Synchronous DRAM applications

Distributes one clock to multiple outputs in a banked mode

External Feedback (FBIN) pin is used to Synchronize the Outputs to the Clock Input

No External RC Network Required

Operates at 3.3-V Vcc

Packaged in Plastic Thin Shrink Small-Outline Package

Series or parallel termination options

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.

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