PHY LAYOUT

This document makes recommendations for the layout of the PHY and Link layer devices in an IEEE 1394 environment. The optimal performance of an IEEE 1394 bus can be dependent on good board layout. An IEEE 1394 board that does not adhere to good layout guidelines may be susceptible to noise and interference which could diminish the signal integrity. This document is not meant to be a general tutorial on good PWB layout practice; it is meant to highlight those areas of a 1394 node that may need special attention due to the special requirements of IEEE 1394 nodes.

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