A LOOK AT BOUNDARY SCAN FROM A DESIGNER'S PERSPECTIVE

While ultimately the decision to use boundary scan test (also know as JTAG or IEEE 1149.1) in a given design should be based on the positive impact to product life-cycle cost, the benefits that accrue to the designer are often overlooked. This document describes the benefits in design verification and debug for designers at all levels of product design: chip, board, and system. It also provides insight into special considerations such as scan chain design and the multidrop problem in backplane-based system test. A comprehensive list of references is included.

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