DESIGN-FOR-TEST ANALYSIS OF A BUFFERED SDRAM DUAL-IN-LINE MEMORY MODULE (DIMM)

This document presents a design-for test (DFT) analysis of a buffered synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM). The analysis is restricted to board-level manufacturing faults. The test problem is defined with a solution presented. Alternate methods are given. A comparative study contrasting a DFT approach using a boundary-scan test vs. a non-DFT approach is presented.

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