CLOCK DISTRIBUTION IN HIGH-PERFORMANCE PCS

High-performance systems demand carefully designed clock generation

and distribution networks. A designer needs to meet tighter timing, lower

power consumption, smaller space, lower operating temperatures, and

lower cost requirements. Timing performance is optimized by reduction

clock skew. This document discusses the different types of skew, power

dissipation, and high-speed design considerations in system clocking

networks.

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.

(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
Trademarks, Important Notice!