SEAMLESS PROCESSOR INTERFACE USING FIFO BUS MATCHING AND BYTE SWAPPING

TI FIFOs, SN74ABT3613 (64 ´ 36) and SN74ABT3614 (64 ´ 36 ´ 2), contain bus matching and byte swapping features in a 36-bit chip. These features eliminate the need for multiple devices and discrete glue logic in hardware designs. This document shows the data manipulation for a DSP-based message system and a CISC-based broadband communications system. In the first, the SN74ABT3617 interfaces the 32-bit TMS320C31 DSP to an 8-bit microcontroller. In the second, the SN74ABT3614 is used for bus matching and byte swapping of data for an Ethernet controller interface to a CISC host processor.

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