SPARC MBUS-TO-FUTUREBUSPLUS BRIDGE USING THE TI FUTUREBUSPLUS CHIPSETThis document describes the logic to connect the SPARC Mbus to the TI Futurebus+ (FB+) chipset host interface (HIF). This logic is a translator of Mbus to HIF transactions and vice versa. Direct and paged-memory are described, along with techniques for a 64-bit-only data path and a dynamically configurable 32-bit Mbus/32-bit HIF or 64-bit Mbus/64-Bit HIF. View the complete PDF document: scaa019a.pdf (59 K Bytes) (Requires Acrobat Reader 3.x) Go to the Engineering Design Center to locate information on other TI Semiconductor devices.
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