ADVANCED LOW-POWER CMOS FIFOS

The architecture of the next-generation microprocessors and DSPs requires less power, possesses higher gate counts, and operates at lower voltage levels with no performance sacrifice. To meet these requirements TI designed a low-power, high performance, 3.3-V FIFO family with both clocked and strobed architectures. This document describes the basic operation of TI’s 3.3-V FIFO Family.

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