FIFO MEMORIES: SOLUTIONS TO REDUCE FIFO METASTABILITY

A metastable event occurs when the output of a logic device is neither a logic high nor a logic low level during a time period. Using a FIFO to synchronize digital signals operating at different frequencies may cause a metastable event to occur. This document assists designers in understanding and improving upon the metastable characteristics of the SN74ACT722xx family of synchronous style devices and increasing their reliability.

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