FIFO MAILBOX-BYPASS REGISTERS: USING BYPASS REGISTERS TO INITIALIZE DMA CONTROL

The TI 32- and 36-bit FIFOs contain mailbox-bypass registers that transmit priority from one FIFO port to the other, port A to B or port B to A with out storing the data in the FIFO SRAM buffer. This document describes the FIFO mailbox-bypass registers and shows an example of direct memory access (DMA) control of a digital signal processor (DSP). The components described are the SN74ACT3641 and the 32-bit floating-pointTMS320C31 DSP.

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