INTERFACING TI CLOCKED FIFOS WITH TI FLOATING-POINT DSPS

FIFO memories are used in digital signal processing systems for matching data paths with asynchronous clock or data rates. This document shows the SN74ACT3632 512´36´2 clocked FIFO as a single-chip bi-directional buffering solution that interfaces to the TI TMS320C3x and TMS320C4x floating-point DSP family. Programmable FIFO flags enable DMA control techniques that are used to handle the data flow. A detailed design example is given for the SN74ACT3632 and the TMS320C31-40. The SN74ACT3632 interfaces to DSP busses operating up to 67 MHz.

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