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Mass Storage Technology Fact Sheet
Redefines DSP for Mass Storage WorldWith the new TMS320C27x DSP, Texas Instruments introduces a breakthrough architecture that unites the flexibility, ease of use and cost-efficiency of an MCU with the high performance of a DSP — all in a single device. The ’C27x architecture has been custom built from the ground up to address the specific requirements of high-performance, high-precision mass storage electronics. This all-platform uniprocessor combines the efficient C language compiling, interface control and ease of programming capabilities found in the most advanced MCUs with the precise servo/spindle control of DSPs.TI’s ’C27x architecture features the best from both technologies, combining 100 MIPS of DSP performance with traditional MCU strengths of ease of software development, compactness of code and flexibility of interrupt handling. By incorporating this level of functionality, flexibility and power in a cost-effective, single-chip solution, the new ’C27x-based DSPs pro-vide a future-ready solution to the ever-increasing performance and time-to-market demands of tomorrow’s sophisticated mass storage applications. The ’C27x core provides performance for advanced systemsUsing TI’s 0.25 micron CMOS process, the ’C27x core is embedded in the ASIC back-plane for custom digital mass storage solutions. The core provides 100 MIPS of calculating power at 100 MHz, 5x the performance of any MCU currently in use for storage applications. TI plans to migrate the 'C27x to its 0.18 micron TImeline technology and 150 MIPS in late 1998. This advanced level of power provides today’s customers with areal density leadership at a reasonable cost. Beyond this, it enables drive engineers to accommodate future performance requirements brought on by emerging technologies, like microacuators, very high-speed motors, high-speed interface and 8x or greater DVDs. TI’s low cost development path for the 'C27x will carry designers through multiple product cycles without a major investment in firmware.The new TI 'C27x DSP core utilizes a modified Harvard architecture that can be addressed as a single software stack for Von Neumann operations. It features two data read busses and an instruction read bus, with several enhancements aimed at improving code density and performance in interrupt-driven applications in the storage industry. Offering the power of a high-performance RISC micro-processor, the core is optimized for real-time control and data processing in storage applications, providing an ideal computing engine for advanced controller development. It is completely compatible with advanced all-digital CMOS read channel technology, keeping the drive designer well ahead of the curve in the bits-per-inch race. The 'C27x provides this level of performance at no additional cost in hardware, opening the door for developers to take optimum advantage of the DSP’s advances in integration and power. Furthermore, it opens the door for the design team to focus on creating product innovation and differentiation that will drive the future of storage product electronics. Industry-leading code efficient architectureOptimized for both servo and interface system control, the 'C27x architecture features efficient addressing modes and specialized instructions that combine to produce the highest level of code compactness in the industry. More compact code executes faster, consumes less power and reduces memory cost.To help maintain this level of code density, the 'C27x architecture has been designed to utilize read-modify-write operations. A single instruction directs the processor to read data from memory, modify it and write it back to memory. Virtually all MCUs require three or more steps to perform this common embedded system I/O operation. This single, or atomic, instruction provides a distinct advantage over traditional load-store or RISC architectures because it generates less code, executes the code faster and protects the operation from being corrupted by interrupts. With the 'C27x devices, these logical or arithmetic operations can be performed on any memory location. In developing the 'C27x architecture, existing firmware code for all major drive manufacturers was closely examined. Virtually all of the most commonly used instructions were implemented as part of the 'C27x’s final instruction set, allowing drive designers to work as they have with previous generations of less capable MCUs. TI has also developed a family of tools to port existing legacy code to this new platform to further reduce development time and costs. Architecture Feature SummaryGeneral features
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