Digital Signal Processing Solutions Products - TMS320C54x

New TMS320C54x DSPs from TI Combine Industry's Lowest Power Dissipation with Highest Performance in Smallest Space

TMS320C549 and TMS320C5410 - Technical Fact Sheet

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Lowest Power Dissipation in the Industry

• .45 milli-Amps per MIPS or 113 Milli-Watts at 100 MIPS
• 'C5410 core operates at 2.5V with 1.8V core planned
• Integration of large memory and peripherals reduces power-consuming off-chip operations
• Power-reducing features include
  • Three IDLE states drop power to less than one micro-Amp
  • External bus-off control disables the external bus
  • Bus keepers/holders maintain the last state of the external bus
  • Software-programmable phase lock loop (PLL) lowers system clock

Large Memory Integration

• 'C549: 32K words of on-chip SRAM
• 'C5410: 64K words of on-chip SRAM

Small Packaging

• 'C549 and 'C5410 are available in a 144-pin package, measuring 20 x 20 x 1.4 mm for easy upward migration
• 'C549 also comes in a 144-ball microStar™ BGA package measuring 12 x 12 x 1.4 mm (smaller than a U.S. dime)
• 'C5410 will also initially be offered in a microStar BGA package (176 balls) measuring 15 x 15 x 1.4 mm
• microStar BGA can use laser-drilled vias for ultimate reduction in effective footprint

New Peripherals on 'C5410

• Multi-Channel Buffered Serial Port (MCBSP)
  • Double buffered data registers allow continuous data stream
  • Full-duplex, bi-directional communication
  • Direct interface to T1/E1 framers, MVIP, ST-bus and IOM-2 devices
  • Multi-phase frame synchronization for interfacing to AC97 devices
  • Multi-channel transmit and receive of up to 128 channels
  • Highly programmable internal clock and frame generation
• Direct memory access (DMA) channels
  • Six DMA channels provided: one with 23-bit and five with 16-bit address capabilities
  • Accessible to program, data and I/O spaces
  • Programmable priorities for each channel
  • Five options for source and destination address modifications
  • DMA transfer can be synchronized with MCBSP transmits or receives, timer interrupt or INT3
  • Double word (32-bit) mode
  • Multi-frame transfer mode available for each DMA channel

Small Assembly Code Size

• Highly efficient dual-operand instruction set working in tandem with two read buses, one write bus and one program fetch bus
• 40-bit adder and two 40-bit accumulators support parallel instructions that execute in only one instruction cycle
• Single-cycle instructions that efficiently execute common DSP tasks that required multiple instructions on previous DSPs
• 40-bit ALU features a dual 16-bit configuration capability to enable dual one-cycle operations

Trademark:
microStar is a trademark of Texas Instruments Incorporated.