TMS320C3x Simulator

The simulator provides cost-effective application development and program verification in non-real-time. Each of the simulator's software programs simulates C3x operation and allows monitoring of the state of the processor. Simulation speed is typically on the order of hundreds of instructions per second on a PC.

Key features of the C3x simulator -- and common to all TMS320 software simulators -- include:

• Execution of user-oriented DSP programs on a host computer
• Modification and inspection of registers
• Data and program memory modification and display:
  • Modification of an entire block at any time
  • Initialization of memory before a program is loaded
• Simulation of peripherals, caches, and pipelined timings
• Extraction of instruction cycle timing for device performance analysis
• Programmable breakpoints on:
  • Instruction acquisition
  • Memory reads and writes(data or program)
  • Data patterns on the data bus or the program bus
  • Error conditions
• Trace on:
  • Accumulator
  • Program counter
  • Auxiliary registers
• Single-stepping of instructions

The Simulator offers the following additional features to the TMS320 Debugger Interface :

• Memory-mapped I/O can be connected to a host file to simulate I/O such as synchronous serial port I/O.
• The simulator can simulate external interrupts.
• It can monitor the opcode and address at each phase of the pipeline with 8 pseudoregisters.

TMS320C3x Simulator

The C3x Simulator is a software program that uses the host processor and memory to perform instruction- and C-level simulation of the C3x DSP. It essentially provides XDS510 software debug capability for a C30 or C31 plus external memory without the DSP hardware. Since the host is used to simulate the C3x, a program will run more slowly with a Simulator than with an EVM or XDS510.

The Simulator offers the following additional features to the TMS320 Debugger Interface:

• Memory-mapped I/O can be connected to a host file to simulate I/O such as synchronous serial port I/O.
• Simulate external interrupts.
• Monitor the opcode and address at each phase of the pipeline with 8 pseudoregisters.