The following is a list of all currently known Defects in the current release of the Code Generation Tools. All defects will be fixed in the next release unless otherwise indicated.

Note:

This list may contain references to internal or beta versions of the product. So please refer to product availability list to determine the current production revision.

Date: Fri Sep 27 19:00:00 CDT 1996

ANSI C Compiler

Assembler

C I/O

Debugger

Documentation

emurst

Hex Converter

Linker

PDM

RTS

ANSI C COMPILER DEFECTS

ppcg and mpcg abnormally terminate when presented with a switch case constant
which is unsigned and has the high bit set.
 
Example:
 
void test(unsigned int b)
{
   switch(b) {
     case 0x81000001:
     break;
     case 0x41000001:
     break;
   }
}

None.

   The compiler errs in generating an reti1 instruction in parallel
with an instruction which modifies the stack on return from an
interrupt service routine generated using the "interrupt" keyword
in C source. Since the reti1 mnemonic is representative of the
instruction "sr = *sp++" so this renders the instruction sequence
shown below as :  sr = *sp++ || d0 = &*(sp ++=4) . This sequence
will cause the stack to be corrupted, since the incerement is not
performed before sr gets popped off the stack.
 
   i.e. code sequence generated by compiler at return from interrupt
 
             reti1
    ||         d0 = &*(sp ++= 4)
             reti2
             reti3
             reti4

   Modify the code generated by the compiler to perfom the stack
increment before sr is popped.
 
    i.e.
           d0 = &*(sp ++=4)
           reti1

When using mpcl from the command line with a large number of defines, mpcl
fails and reports "abnormal termination of mpac."
 
Example:
mpcl -g  -ft /tmp -dAZZZZZZZZZZZZZZZ -dBZZZZZZZZZZZZZZZZZZZ \
 -dCZZZZZZZZZZZZZZ -dDZZZZZZZZZZZ -dEZZZZZZZZZZZZZZZZZZ \
 -dFZZZZZZZZZZZZZZZZZZZZ -dGZZZZZZZZZZZZZZZZZZZZ \
 -dHZZZZZZZZZZZZZZZZZZZZZZ -dIZZZZZZZZZZZZZZZZZZZ \
 -dJZZZZZZZZZZZZZZZZZZZZZZZ -dKZZZZZZZZZZZZZZZZZZZZ \
 -dLZZZZZZZZZZZZZZZZZZZ -dMZZZZZZZZZZZZZZZZZZZZ \
 -dNZZZZZZZZZZZZZZZZZZZZZZZZ -dOZZZZZZZZZZZZZZZZZZZZZZZZZZ \
 -dPZZZZZZZZZZZZZZZZ -dQZZZZZZZZZZZZZZZ  -dRZZZZZZZZZZZZZZZZZZZ \
 -dSZZZZZZZZZZZZZZ -dTZZZZZZZZZZZ -dUZZZZZZZZZZZZZZZZZZ \
 -dVZZZZZZZZZZZZZZZZZZZZ -dWZZZZZZZZZZZZZZZZZZZZ  -dXZZZZZZZZZZZZZZZZZZZZZZ \
 -c test2.c -z link.cmd -o test.out

Move the defines inside the source file.

See table on CG:5-27.
 
Both minit() and ltoa() are defined, and listed in the CodeGen manual,
but neither is declared in stdlib.h, as they should be.

The problem will be fixed in the next release.
There is no workaround.
 

When declaring several large initialized arrays, the compiler will sometimes
generate an error:
 
   The following symbols are undefined:
     VRxx
 
Large arrays may cause instruction to be generated
which use "virtual registers" which are internal to
the compiler.

The problem may be avoided by making large arrays static.

The PP C compiler will produce incorrect assembly output on the following
C code segment when optimization is used:
 
C code segment:
   if ( out < 0 )
      out = 0;
   else if ( out > 0xFFF )
      out = 0xFFF;

None.

Input line buffer for DOS was 2K, because of 640K memory limit.
ANSI requires only 512 bytes, but the documentation states a limit of
16K.

None.

ppcg and mpcg abnormally terminate when presented with a
switch case constant which is unsigned and has the high bit set,
 
Example:
 
void bad(unsigned int b)
{
   switch(b) {
     case 0x81000001: /* Causes abnormal termination: high bit set */
     break;
   }
}
 
void good(unsigned int b)
{
   switch(b) {
     case 0x41000001: /* Doesn't terminate: high bit not set. */
     break;
   }
}

None.

There is a general problem when data is at a location in
static data that is greater that 32767 bytes away for 32 bit
or 16 bit data items and 65535 bytes away for 8 bit items.
The symptoms of this problem are the message
 
   E0004: Address offset is too big
 
from ppasm in response to the C compiler generating bad code or
 
   COMPILER ERROR: no match for VARADDR
 
from ppcg.
 
An example of a C program that will cause bad code to be
generated is
 
  int ar1[35000];
  int ar2[35000];
 
  void f1()
  {
 
     extern int *v1;
     extern int *v2;
 
     v1 = &ar1[0];
 
     v2 = &ar2[0];
 
  }
 
An example of a C program that will cause a compiler
internal error is
 
  int ar1[45000];
 
  void f1()
  {
     extern int *v1;
 
     v1 = &ar1[32768];
 
  }
 

none

Initialization of a string field whose length is greater than 1 and
is followed by another field which is initialized as well, may
have incorrect assembly code generated.  For example
 
struct problem
{
    char cStr[6];
    char cVal;
};
 
struct problem init_me =
{
   "a",
   '5'
};

Initialize the string to string value greater than 1.

The cast of a function call to an integral type, when the
function is defined to return a pointer, results in the
using the return location for an integral value rather
a pointer value.  For example
 
  char *func_return_pointer();
 
  main()
  {
    int_return;
 
    int_return = (int)func_return_pointer();
  }
 
  char *func_return_pointer()
  {
    return (char*)0x10000000;
  }
 
results in an undefined value being assigned to int_return
and the actual function return value being ignored.

The function return vale may be copied to a variable
and the variable used in place of the function call.
For example
 
  char *func_return_pointer();
 
  main()
  {
    int int_return;
 
    int_return = (int)func_return_pointer();
  }
 
  char *func_return_pointer()
  {
    return (char*)0x10000000;
  }
 
may be rewritten as
 
  char *func_return_pointer();
 
  main()
  {
    char *char_tmp;
    int  int_return;
 
    char_tmp = func_return_pointer();
    int_return = (int)char_tmp;
  }
 
  char *func_return_pointer()
  {
    return (char*)0x10000000;
  }

The C compiler optimizer aborts.

none

ASSEMBLER DEFECTS

The illegal use of register R1 as the destination in a floating-point write
does not generate an error message.
 
Example:
 
_main:
         move      040000000h,r3
         move      03f800000h,r2
         fadd.sss  r2,r3,r1
         jsr       r31(r0),r0
 
The floating-point add instruction above should generate an error message,
but does not.

None.
 

The assembler does not allow aMPY||SADD instruction in revision less than
3 silicon.
 
The instruction forms onpage 8-88 such as:
 
        d3 = d1*d2
        || d4 = d6 + d5>>-d0
 
return an "Illegal combination of 6 operand operation" error.  Use the -v3
option to assemble correctly.
 

Perform the shift in a separate instruction.

   In PP assembler if a multiplication and an addition are
done in parallel, the multiplication instruction must be
specified first or the assembler generates an error.
 
  i.e.   d1=d2*d3 || d4 = d5 + d6      <=== works okay
 
         d4 = d5 + d6 || d1=d2*d3      <=== doesnt work

Always specify the multiply instruction first.

The PC NT version 1.13 of ppasm incorrectly assembles the following EALU
instructions (bits 31,27 are 1 instead of 0):
 
       d2 = ealu(d5, d4\\d0, %d0)
     || a8 = d3
     || d7 = &*(-5)
Assembles as: fa1282df instead of 721282df
 
      d3 = ealu(d3, d2\\d7, %d7)
     || d1 = &*(a9 += x8)
     || d2 = &*(a0 += x0)
Assembles as: fbdb5de2 instead of 73db5de2
 
      d2 = ealu(d2, d1\\d0, %d0)
     || d3 = &*(a8 += x9)
     || *a3++ = d3
Assembles as: fa1282df instead of 721282df

Either avoid these instructions, or correct the misassembled bits.

EALU||ROTATE instruction assembles incorrectly.
 
Example:
  d0 = FOO
  d1 = ealu(FOO: d1&~@mf || d5 = d1 \\ 8)
This is assembled incorrectly as: 70092080
                   But should be: 72292880

None.

Ealu instructions are sometimes assembling incorrectly when
appearing without parallel instructions.
 
Example:
 
This Assembles incorrectly without parallel instructions:
temp1_temp2     .set d1
mask            .set d2
test2           .set d4
   test2 =me ealu(MULT_SHIFT:(temp1_temp2\\31&mask)|(@mf&~mask))
 
   Incorrectly assembles as: 70242100
     But should assemble as: 72242100
 
 
   The instruction assembles correctly once parallel instructions are added:
   d0 =r (d0 * d0)<<1
      || test2 =me ealu(MULT_SHIFT:(temp1_temp2\\31&mask)|(@mf&~mask))
      || d0 = d0

None.

  The destination register for a parrallel ealu || multiply
  operation is always assembled as one register number greater.
 
   i.e.  d0=BUG
         d1=ealu(BUG: d1+d1) || d6=d3*d2
 
 
               is assembled as
 
 
         d1=ealu(BUG: d1+d1) || d7=d3*d2

   Reverse the order of the parallel instruction so that the multiply
   instruction appears first.
 
   i.e.    d6=d3*d2 || d1=ealu(BUG: d1 + d1)

Instructions like the following assemble incorrectly:
 
        d3 = ealu(BLAH: d1 | d2 & @mf)
Incorrectly Assembles as:  701B2100
              instead of:  721B2100

WORKAROUND/SOLUTION
===================
 
Replace the sequences such as
 
        d0 = BLAH
        d3 = ealu(BLAH: d1 | d2 & @mf)
 
with
 
        d3 = d1 | d2 & @mf

The following ealu instruction is assembled incorrectly:
 
Assembler produces:
 
Opcode (incorrect): FA1360C4C4528C40
                                  d3 = ealu(TESTDIVIDE:
                                     d1 - (d3\\d0 & %d0) || d2 = d3\\d0 )
                                     || d4 = &*(a2 + x0)
                                     || d3 =ub *(a8 ++= [x9])
 
 
instead of:
 
Opcode (correct): 721360C4C4528C40
                                   d3 = ealu(TESTDIVIDE:
                                     d1 - (d3\\d0 & %d0) || d2 = d3\\d0 )
                                     || d4 = &*(a2 + x0)
                                     || d3 =ub *(a8 ++= [x9])

None.

This bug only applies to PC PP Assmebler:
 
Performing a right shift with the shift amount in a
register causes the assembler to generate the
wrong instruction.  The mask bit in the oper field
when the F bit is set in the D0 code.
 
The assembler seems to give an incorrect opcode no matter what is done
in parallel with this right shift. A few examples follow:
 
 
  d7 = d2>>u -d3
  d1 = d2>> -d4
  d2 = d3>>-d4
       || d1 = &*(-1)
   d2 = d5>>u -d7
       || d3 = *(a10+[2])
 
The code assembles, but when it is loaded into the debugger, weird
symbols are present. The symbols are not consistent, but a common wrong
opcode looks like this:
 
 
         d7 = d2>>u SHAMROCK SHAPE  Square Root Symbol(Heart Shape)
 
         or, another common one is taking the derivative of a Heart,
 
 
The incorrect opcodes are SOMETIMES fatal (and always incorrect) causing
the debugger to hang.

None.

The conditional source selection operator is not
allowed in MPY||ADD instructions.    For example
 
   d1 = d2*d3 || d4 = d5 - d7 [n] d6
 
When the conditional source selection operator appears
the MPY||ADD instruction a "Processor resource allocation
conflict" message is given.

The MPY||ADD instruction may be broken into two parts.
For example
 
         d1 = d2*d3 || d4 = d5 + d7[n]d6
 
would become
 
         d1 = d2*d3
 
         d4 = d5 + d7[n]d6

Legal generic MPY||EALU syntax instructions will not assemble and report
"illegal combination of six-operand instruction error."
 
Example:
        d4 =u d1*d3
            || d6 = ealu(d6,d6\\d0,%d0)

Replace the generic EALU syntax for MPY||EALU with the
explicit EALU syntax.

Parallel transfer formats do not allow labels immediately following
the equal (=) that begin with "g", "m", or "h" because they are being
confused with the assignment modifiers.
 
Examples:
        d4 =h *(a10++=vvar)     ; passes
        d4 =h *(a10++=gvar)     ; fails because of =g
        d4 =h *(a10++=mvar)     ; fails because of =m
        d4 =h *(a10++=hvar)     ; fails because of =h

Place at least one space following the equal in a parallel
transfer.

The three-operand instruction "Di = ealu(label:Dj+Dk+1)" is not
assembled.

There are two workarounds:
 
1. Use an explicit increment instruction on a later cycle after the
   "Di = ealu(label:Dj + Dk)" instruction.
 
2. Use the two instructions
   d0 = label + 0x040000     ; Set bit 18 of D0
   Di = ealu(label: Dj + Dk)

The order of evaluation of expressions is specified in
the user guide in section 8.2.1, pages 8-13 and 8-14.
Expressions other than address expressions are not evalutated
in the specified order.  For example
 
  d3 = 155 - 55 + 45
 
results in
 
  d3 = 55
 
rather than the correct
 
  d3 = 145
 
Operator precedence must be strictly followed.

In order to avaoid the operator precedence problem expressions
may be fully parenthesized.  For example
 
  d3 = 155 - 55 + 45
 
may be specified as
 
  d3 = (155 -55) + 45
 

The use of index registers in an ealu is recognized but when
assembled they are not properly encoded.  An incorrect register
bank is chosen athough the correct register number is used.  For
example in
 
   d0 = MPY_TEST
 
   d1 =u d1 * d4
      || d2 = ealu (MPY_TEST: d2 + x8)
 
index register x8 is encoded as pc.  In the reported test case
 
   d0 = MPY_TEST
 
   d1 =u d1 * d4
      || d2 = ealu (MPY_TEST: d2 + x8)
      || d0 = *(a1 + [5])
 
index register x8 is encoded as its companion register d0.

The contents of the index register may be assigned to a
d register and the d register used in place of the index
register.

Multiplications of the form
 
   d1 = d2*d3 << 2
 
receives the message
 
   E0004: Multiply operands must be D registers

none

Bit operations are performed without regard for operator precedence.
The result is that expressions with bitwise operations may not be
correctly evaluated.  For example
 
        d1 = 0xFFFF
 
        d2 = (d1 & 3) ^ 3
 
        d3 = (d1 ^ 3) & 3
 
The values assigned to d2 and d3 should be identical and the result in d4
below should receive the same value
 
        d4 = 3&~d1
 
the current result is that d2 receives the value 0 and d3 receives the
value of the rightmost 3 bits.

The expression 3&~Dx may be used instead of (Dx^3)&3 or (Dx&3)^3.
In general operations must be separated into simler expressions
with no more than one bitwise operation.

ppasm does not support any EALU||ROTATE subfunction with a -1 in it.
See Table 4-2 on PP: 4-21.
 
Functions that do not assemble:
-1
-B-1
-C-1
-(B&C)-1
-(B|C)-1
-(B&~C)-1
-(B|~C)-1
(B&~C)|((-B-1)&C)
(B&C)|((-B-1)&~C)

-x-1 is equivalent to ~x.  Make this substitution accordingly to make the
assembler accept the instruction.
 
Equivalent functions:
-1 (no workaround)
-B-1               ~B
-C-1               ~C
-(B&C)-1           ~(B&C)
-(B|C)-1           ~(B|C)
-(B&~C)-1          ~(B&~C)
-(B|~C)-1          ~(B|~C)
(B&~C)|((-B-1)&C)  (B&~C)|(~B&C)
(B&C)|((-B-1)&~C)  (B&C)|(~B&~C)

Inserting a zero inside of an EALU function often causes the
assembler to fail.  If one of the two subfunctions is unused, it
is not necessary to insert a zero.
 
Example:
 d5 = ealu(test1: d1&((d2\\d3)&d4)) ; this will pass
 d5 = ealu(test1: d1&((d2\\d3)&d4)+0) ; this will fail

None.

EALU doesn't support subfunctions (B&~C)|(~B&C) and (B&C)|(~B&~C).
 
If f1 or f2 is either of these, assembler returns error:  Unable to match
EALU explicit expression to a d0 code
 
Examples:
         d0 = ealu(test: d0&((d0\\d0)) + ((d0\\d0)&~d0)|(~(d0\\d0)&d0))
 

None.

Any instruction of the forms below cause the assembler to report an
error (including ~@mf, ~(src1\\src3), etc.):
 
dst = ealu(label: src2 + ((src1\\src3)|@mf) + (src1\\src3))
dst = ealu(label: src2 + ((src1\\src3)&@mf) + (src1\\src3))

None.

Assembler reports an error in instructions like the following which use
the mask generator (%src4) (including forms with ~(src1\\src3), ~%src4, etc.):
 
dst1 = src2 + ((src1\\src3)&%src4 + (src1\\src3))
dst1 = src2 + ((src1\\src3)|%src4 + (src1\\src3))
 
Note that the assembler only complains if there is no C port (%src4)
present on the left hand function f1(b,c).

None.

Assembler does not support the minus 1 subfunction.  When it sometimes works,
it misassebles the function using a 15-bit immediate instead of the ALU
subfunction.
 
From PP User's Guide page PP:4-21
 
output = A & f1(B,C)+f2(B,C)
 
If f1=-1 or f2=-1, the code will not assemble correctly.
 
Examples:
         d0 = ealu(test2:d2&-1 + d3)
 
 
 

None.

 
If a non-D register is used as dst2 (as x2 is used below), the assembler
will crash with a Segmentation Fault.
 
Example:
 d3 = ealu(test22: d1&((d2\\d1)) + (d2\\d1) || x2 = d2\\d1)
 

None.

The retiN commands are not assembled correctly in the
beta release nor were they correctly assembled in release
1.10.

none

Directives .struct, .tag and .union do not force alignment on
32 bit boundaries.  They only force 8 bit alignment.  This means
that structures/unions containing elements requiring speific alignments
may be aligned on any boundary.  This will cause memory access failures.

Place directives of the form
 
         .align 32
 
before .struct, .tag and .union directives.

Specification of ealuf via the "ealuf" keyword is ignored.  When ealuf is
needed, it can be generated by writing two ealu functions with the same label,
where one ealu function is the inverse of the other as in Example 2 below.
 
Example 1:
  d1 = ealuf(label1: d2+d3) ; Assembles incorrectly and ealuf is ignored.
  d1 = ealuf(d1,d2\\d3,%d0) ; Assembles incorrectly and ealuf is ignored.
 
Example 2:
  d0 = label3
  d2=d3*d4 || d1 = ealu(label3: d2+d3>>0) ; Assembles correctly as ealu
  d2=d3*d4 || d1 = ealu(label3: d2-d3>>0) ; Assembles correctly as ealuf

none

Different protection bit settings are allowed on parallel commands.
This should be reported as an error.  For example
 
  lctl =[.n] ealu(test2306: -1 || d2 =[.nvc] d1\\d7)
 
should receive an error message since "[.n]" and "[.nvc]" are not
the same.

Specify the protection bits identically on all parallel
commands.

C I/O DEFECTS

There is a bug in the cio code involving cio writes to the host. If
the first write to a stream is larger than 256 bytes, memory in the
target and the host will be overwritten. This bug affects the function
fwrite.

Make sure the first write to a stream is less than 256 bytes, all subsequent
writes to that stream, regardless of size, should work correctly.
 
For example:
 
fwrite(buffer,sizeof(char),16384, fptr);
 
will break, but
 
fwrite(buffer, sizeof(char), 1, fptr);
fwrite(buffer, sizeof(char), 16383, fptr);
 
will work ok.

DEBUGGER DEFECTS

When a breakpoint is set in a file with a very long path set with the "use"
command, listing the breakpoints with bl does not display all breakpoints.

Make a soft link to the directory which will shorten the number of characters
in the path.  Then add "use linkname" instead of "use very/very/long/path" to
the init.cmd file.

The TCOUNT register is not accurately simulating the number of clock
cycles when external memory is being accessed.  This is also exhibited in
the runb command returning incorrect values in the clk register.

Do not trust TCOUNT or CLK if accessing external memory or when issuing
transfer controller packet requests.

When PP simulators are spawned before the MP simulator, the MP simulator
may crash.
 

Start MP simulator before PP simulators.

Subtraction in address offset expressions does not
always produce a correct result.
 
Example:
   d1 = d1 + 1 || d3 = a4 || *(a0 - 9) =b d4
disassembles as:
   d1 = d1 + 1 || d3 = a4 || *(a0 - 1) =b d4

None.

The MP simulator contains a bug that can cause it to incorrectly execute
an MP instruction of the form "st -64(r2:m),r2."  When the simulator attempts
to execute this instruction, it incorrectly increments the value of r2 before
writing r2 to memory; the increment is supposed to follow the write.
 

None.

The dst and dld commands are supposed to behave identically to st and ld
when accessing on-chip memory.  When viewing in the memory window the on-chip
location stored by dst, the value at the stored location never gets updated.
But simulation is still performed correctly.  If the location is read with
a ld or dld, the correct value is read.
 
Example:
 
        addu 0xff,r0,r13
        st   0x1010004(r0),r13
 
At this point, location 0x1010004 contains the value ff in the memory window.
 
        addu 1,r0,r13
        dst  0x1010004(r0),r13
 
Here, the memory window incorrectly still displays the old value ff.
 
        dld  0x1010004(r0),r14
 
But here you can see that the simulator actually behaves correctly
internally, because r14 contains the expected value: 1.

Use st and ld when accessing internal memory.

Single stepping C code is too slow.

None.

Typing sconfig alone is supposed to restore the screen configuration stored
in init.clr which is either in the current directory or the D_DIR
environment variable.  The PC version 1.13 does not look for the file and
returns an error if no filename is supplied.

Save the screen configuration before making any changes with the command
"ssave".  Then "sconfig" by itself will load the default screen configuration
from the file "init.clr".
 

PP code submits packet transfer suspension by sending "S" bit.  However,
PP continues with ongoing packet transfer.
 

If Q is active when packet suspension is submitted, and "S" bit in
the COMM register is set, Q goes to ZERO and P set to
1 automatically(S = 1, Q = 0, P = 1) informing linked-list suspended,
Q was still active.
 
In the simulator, P = 1  triggers the packet transfer eventhough
the S bit is set to ONE. That is the bug.
 
As a workaround, if P is made ZERO(S = 1, Q = 0, P = 0) after
the instruction which sets the S bit to 1 will suspend the
packet transfer.
 
To resume the packet transfer from the point where it was
suspended, set S = 0, and P = 1.
 

Goto /net/magoo/home1/karen/c80hotline/take_color.sdb
 
Will fix next release

WORKAROUND/SOLUTION
===================
 
Load colors in manually, not from init.pdm

When target board power is not connected, starting the debugger causes a
crash, reporting a program exception error.

Make sure power is connected to the target board when starting the debugger.

When the operation dX =b *(aY-Z) is combined with certain parallel
instructions, the address offset (Z) is not displayed in the disassembly
window.  An example instruction causing the problem is:
 
 *a0 = d0 || d1 =b *(a8-8)
 
which disassembles incorrectly as:
 
 *a0 = d0 || d1 =b *(a8)

Please ignore the incorrectly displayed disassembly.  Code is assembled
correctly.  For debugging purposes, the operation with the address offset
can be placed in an instruction by itself.

Just prior to entering main(), when a variable has not yet become valid,
the watch window displays the uninitialized value in a color which indicates
that the variable is valid.  (Default invalid color is red.)

Ignore color information in watch window when just entering the beginning of
main().

In the MP SDB Debugger, 2 consecutive reset commands will cause the
debugger to get a processor access timeout error.

Perform a single-step between reset commands.

Debugger displays incorrect values for double floats with the WA and
DISP commands.

None.

When packet transfers/external memory accesses are occurring,
clock cycles as recorded by tcount are extremely inaccurate on the
simulator.
 

None.

When using the ms command on the simulator, the following error occurs when
trying to load the output file:
 
mvp1_pp0> load output.dat
Loading output.dat
Object file endianess conflicts with target
Check memory map

The following program can be run to patch the saved file to the correct
endianness.
 
Compile and run this program with the saved file as the argument.
 
/*********************************************************/
#include 
 
FILE *srcfile;
 
main(int argc, char *argv[])
{
   if ((srcfile = fopen(argv[1],"r+b")) == NULL)
   {
      printf("Error opening [%s]\n", argv[1]);
      exit(1);
    }
 
   printf ("Patching [%s] ...\n",argv[1]);
 
   fseek(srcfile,18,0);
   fputc(0x2,srcfile);
 
   fclose(srcfile);
 
}
/*********************************************************/
 
 

When doing a WA args on the following code, the debugger exits:
 
void ppfunc(long *args) {
  int i;
  long x,y,z;
 
  x=*args++;
  y=*args++;
  z=*args++;
 
  for(i=0;i<1;)
    ;
}

None.

Exclusive Range Breakpoint Enable not working correctly with C80 emulator
version 1.10.  The emulator allows user to modify parameters for the
exclusive range breakpoint but transitions to a 'Breakpoints disabled' state
when the parameters are entered(OK'd).

Use inclusive breakpoints as a work-around to this problem.

 
If you declare a very large multidimensional array the debugger does not
handle it properly.  This is best explained with an example.  Let's say
you have the following global variable declaration in a C file.
 
#pragma DATA_SECTION( pp_data, "mysection" )
 
unsigned char pp_data[ 4 ][ 0x1c200 ];
 
You also have the following statements in your link file.
 
MEMORY
{
       MYMEM:  o=0x02600000    l = 0x00100000
}
 
SECTIONS
{
       mysection:      >MYMEM
}
 
If this is all you had in "mysection", the following expressions would
yield:
 
       &( pp_data[ 0 ][ 0 ] ) = 0x02600000
       &( pp_data[ 1 ][ 0 ] ) = 0x0261c200
       &( pp_data[ 2 ][ 0 ] ) = 0x02638400
       &( pp_data[ 3 ][ 0 ] ) = 0x02654600
 
If you type the following statements into the debugger, you will get a
different answer.
 
? &( pp_data[ 0 ][ 0 ] )       ==> 0x02600000
? &( pp_data[ 1 ][ 0 ] )       ==> 0x0260c200
? &( pp_data[ 2 ][ 0 ] )       ==> 0x02618400
? &( pp_data[ 3 ][ 0 ] )       ==> 0x02624600
 
The linker generates the correct addresses, but the debugger computes
the wrong addresses because it only uses the least significant 16 bits
of the 2nd dimension size.
 

Instead of decalring the array with the large dimension second, declare the
large dimension first.
 
i.e. instead of:
  unsigned char pp_data[ 4 ][ 0x1c200 ];
 
use:
  unsigned char pp_data[ 0x1c200 ][ 4 ];

Load and sload on the Workstation Debugger are unnecessarily slow.

None.

The keyboard shortcut "E" in the analysis menu is ambiguous.  It can mean
Exclusive Range Enable or EMU0 driven low.

Use the mouse to select these options.
 

The PC debugger's maximum window width is not wide enough to display all
PP assembly instructions.  For instance, if a PP instruction is using all
four slots (MPY, ALU, Global transfer, Local transfer), the debugger
dissassembly window cuts off the entire local slot.

None.

DOCUMENTATION DEFECTS

   The code generation example in the Code Generation Tools UG (CG:14-1
thru CG:14-27) contains the following error:
 
    The call to memtrans in files pow4.c, sum.c, fib.c, and
    fact.c call memtrans with incorrect types.  These files
    incorrectly assume memtrans is prototyped as
    memtrans(int *, int *, int).
 
    However, the function memtrans is correctly prototyped
    in mvp.h as: char *memtrans(char *, char *, int).
    Therefore, the compiler complains of type mismatch on the
    arguments.
 
 

   Cast the arguments passed to the memtrans function in files pow4.c,
   sum.c, fib.c, and fact.c as char *.
 
     i.e. in file fact.c CG:14-11
 
          memtrans(comm_fact, onchip, sizeof(comm_fact));
 
                     becomes
 
         memtrans((char *)comm_fact, (char *) onchip, sizeof(comm_fact));

The online documentation CD does not work under Windows 95 and Windows NT.

Follow the steps below and you should be able to view the C8x online reference
CD from within Windows 95.  The steps below will assume that your CD is D:\.
 
1. From Windows 95 open up a DOS window.
 
2. Add the lines:
        SET TEMP=C:\TEMP
        SET FULLTEMP=C:\TEMP
   to your AUTOEXEC.BAT file.
 
3. There is a file on the CD, d:\refset\iview.ini .  Copy this file
   to your Windows directory.  You need to edit this file.  At the beginning
   of the ini file there are directions on how to do this.
 
4. This is the crucial step.  Change to the Windows\system directory.
   Create a file named 'win32s.ini'.  This is a text file and should
   contain nothing (blank).  It is the existance of the file that matters.
 
5. Type:
        CD D:\REFSET
   then type:
        GO
   If everything went ok, Iview should appear.
 
Note: For Windows NT, do steps 1, 2, 3, and 5 but don't worry about step 4.

In version 1.13 of the development tools, the README file states that
30 Mbytes of disk space is required for installation.

10M of available disk drive space is sufficient for a complete
installation on the PC version, and 20M is sufficient for the
Sun version.
 
 

The Code Generation Tools Guide does not document the fact that the
simulators do not support the traps for illegal instruction and memory
fault.

None.
 

The assert() macro does not output a message as documented in the Code
Generation Tools User's Guide pages CG:5-15 CG:5-23 and, but simply
terminates the program.

Programmers may insert a printf() inside the assert() macro, but must
be careful to avoid confusion with both MP's and PP's printing diagnostic
error messages simultaneously.
 
You may redefine assert by instead of including assert.h, define assert
as follows:
 
#include 
#define assert(expr) { \
        if(!(expr)) { \
                fprintf(stderr,"Assertion failed, file: %s, line: %d\n", \
                  __FILE__,__LINE__); \
                exit(1); \
        } \
}
 

Debugger command-line access to analysis functions is undocumented.  This
is needed to establish analysis breakpoints to be used in take files.

3.0 Pseudo Analysis Registers
 
3.1 MP & PP ANAENBL Analysis Enable
 
    This register is utilized to enable analysis and select EMU0/1 trigger out
    for a processor.
 
    bits [1:0] => 0x3 to enable analysis
 
    bit   2    => 1 to enable automatic rearm of analysis prior to execute
                  command. (This bit is automatically set when using analysis
                  menu to enable analysis)
    bit   4    => EMU0 trigger out select
    bit   5    => EMU1 trigger out select
 
3.2 MP ANACONFIG
 
    This register is utilized to select breakpoint comparator configuration,
    bus selection, and access qualifications.
 
    bit 0 => 0
    bit 1 => 0
 
    bit 2 => Breakpoint 1
    bit 3 => Breakpoint 2
    bit 4 => Range Breakpoint
    bit 5 => EMU0 driven low
    bit 6 => EMU1 driven low
 
    bit 7  => 0
        .  => 0
        .  => 0
    bit 23 => 0
 
    bit 24 => Comparator 1 bus select ( 0 = Program bus, 1 = Data bus)
    bit 26,25 => Comparator 1 bus qualification
                 00 Read or Write
                 01 Read only
                 10 Write only
                 11 Invalid
    bit 27 => Comparator 2 bus select ( 0 = Program bus, 1 = Data bus)
    bit 29,28 => Comparator 2 bus qualification
                 00 Read or Write
                 01 Read only
                 10 Write only
                 11 Invalid
    bit 30 => Single Point(0)/Range(1)
    bit 31 => Inclusive(0)/Exclusive(1)
 
    NOTE: If you select the Program bus with write only qualification the
          breakpoint will never occur.
 
3.3 PP ANACONFIG
 
    This register is utilized to select breakpoint comparator configuration,
    bus selection, and access qualifications.
 
    bit 0 => 0
    bit 1 => 0
 
    bit 2 => Breakpoint 1
    bit 3 => Breakpoint 2
    bit 4 => Range Breakpoint
    bit 5 => EMU0 driven low
    bit 6 => EMU1 driven low
 
    bit 7  => 0
        .  => 0
        .  => 0
    bit 22 => 0
 
    bit 23,22 => Comparator 1 bus select
                 00 Program Bus
                 01 Global Bus
                 10 Local Bus
                 11 Invalid
    bit 25,24 => Comparator 1 bus qualification
                 00 Read or Write
                 01 Read only
                 10 Write only
                 11 Invalid
    bit 27,26 => Comparator 2 bus select
                 00 Program Bus
                 01 Global Bus
                 10 Local Bus
                 11 Invalid
    bit 29,28 => Comparator 2 bus qualification
                 00 Read or Write
                 01 Read only
                 10 Write only
                 11 Invalid
    bit 30 => Single Point(0)/Range(1)
    bit 31 => Inclusive(0)/Exclusive(1)
 
    NOTE: If you select the Program bus with write only qualification the
          breakpoint will never occur.
 
 
3.4 MP & PP ANASTATUS Analysis Status
 
    This register indicates the state of events that are enabled with bits 2,
    3, and 4 of the ANACONFG register. During a run, if an event is taken,
    that event's bit in the status register is cleared. In other words, the
    exclusive or of bits 2,3 and 4 of the ANACONFIG and ANASTATUS bits indicate
    that an event has occurred.
 
    bit 0 => 0
    bit 1 => 0
    bit 2 => Breakpoint 1
    bit 3 => Breakpoint 2
    bit 4 => Range Breakpoint
    bit 5 => EMU0 driven low
    bit 6 => EMU1 driven low
 
3.5 MP & PP BRK1 BRK2 Address
 
    The brk1 and brk2 registers are utilized to set hardware breakpoint
    addresses.
 
3.6 Analysis Programming Example
 
    To program the analysis module for Single breakpoint type the following
    commands on the command line.
 
    >?anaenbl = 1
    >?anaconfig = 4
    >?anastatus                (should report back 4)
    >?brk1 = 0x02000020 (or any address in your program)
    >run                (processor will halt when breakpoint taken)
    >?anastatus                (should report back 0 - bit 2 cleared)
 

In Table 2-1. TMS320C8x C Data Types, on page CG:2-6 in the MVP Code
Generation User's Guide (SPRU108A), there is an error.  The fourth line
under the "Type" column should read "unsigned short" rather than
"unsigned character".  All other information in the table is correct.

None.

The Multitasking Executive manual states on P. EX:1-9 paragraph 5, "some
developers may elect to disable the kernel's software error checking to
eliminate unnecessary runtime overhead."  It is not explained how this
is accomplished.

The only way to accomplish this is by editing the source code to the
Executive and remove all code that performs error checking.  Search
for all areas of code that contain "TASK_ERROR" and modify the code
accordingly.

The cd (change directory) debugger command is not documented.

The cd (change directory) command is available from the debugger command
line, and will change the current working directory for loads and saves.
Also, cd by itself will print the current working directory.

The fact that the simulator does not support revision 3.x silicon is
undocumented.  If PP code needs to be assembled with the -v3 option, this
code will have unpredictable results when run on the simulator.  Other
uses of revsion 3-specific features will also not simulate correctly.

None.  The new simulator which will support revision 3 silicon will be
released in the coming months.
 

Page PP:15-31 Section 15.2.4.4 of the Parallel Processor User's Guide gives
an example (Example 15-14) that will not assemble.
 
   d0 = h1add_h0subd7 =m ealu(TEST: d6 + ((d5 & ~%%16) | (-d5 & %%16)))
 

Do not use the immediate form of the instruction.  Store the value in a
register and access it like:
 
  d0 = TEST
  d7 =m ealu(TEST: d6 + ((d5 & ~%%d4) | (-d5 & %%d4)))

There are errors in the TMS320C80 to TMS320C82 Software Compatibility User's
Guide on Page 1-7 (Figure 1-1), and Page 1-12.

1. Page 1-7 (Figure 1-1) Memory addresses starting at PP2 data RAM 2 and
   going to the end of the page are incorrect and need to be changed as
   shown below:
 
RAM Block               incorrect address             correct address
-------------           -----------------             -------------
PP2 data RAM 2 (start)  0000 8000                       0000 A000
  "            (end)    0000 87FF                       0000 A7FF
Reserved       (start)  0000 8800                       0000 A800
  "            (end)    0000 8FFF                       0000 AFFF
PP3 data RAM 2 (start)  0000 8000                       0000 B000
  "            (end)    0000 87FF                       0000 B7FF
Reserved       (start)  0000 8800                       0000 B800
  "            (end)    0000 8FFF                       0000 BFFF
 
2. Page 1-12 (First Paragraph) delete "(PP1's in this case)"
 
3. Page 1-12 (First Paragraph) change "010017FCh in the `C80 and to address
   01001FFCh in the 'C82" to "0100#7F0h in the `C80 and to address
   0100#FF0h in the `C82"

Tables 4-2 and 8-27 do not correctly document the last two function
codes in the tables.  They should read as follows:
 
f1  f2  Subfunction     Common Use
----------------------------------------------------------------------
--  3C  (B&~C)|(-B& C)  Choose B if C = all 0's and -B if C = all 1's.
--  C3  (B& C)|(-B&~C)  Choose B if C = all 1's and -B if C = all 0's.
 
Note that (-B-1) should be (-B) and note the fact that these function
codes cannot be used as f1 codes.
 
The following two functions are not supported by the assembler, but can
be coded by hand.  Ensure that the E bit is not set in d0 if you wish to
hand-assemble these functions:
 
f1  f2  Subfunction     Common Use
----------------------------------------------------------------------
28  3C  (B&~C)|(~B& C)  Choose B if C = all 0's and ~B if C = all 1's.
82  C3  (B& C)|(~B&~C)  Choose B if C = all 1's and ~B if C = all 0's.

None.

EMURST DEFECTS

Emurst does not keep the window open long enough to determine if it
was successful.
 

 
Create the following file:
 
-- [EMURST.BAT] --------------------------------------------------------------
 
@echo off
emurst -p%1
if not errorlevel 1 goto Pass
:Fail
pause
goto Pass
:Pass
 
------------------------------------------------------------------------------
 
  If the reset is successful, the window will close immediately. If it fails,
the window will stay open until you press a key.  Also, this
adds the ability to pass the I/O address as a parameter from the icon
properties window.  No, the EMURST.EXE does not have a problem with "-p" if you
don't pass it a parameter. It still defaults to 240. You could put the "-p" in
the properties if you like.
 
 
-- [EMURST Icon Properties] --------------------------------------------------
 
      Description: EMURST
     Command Line: EMURST.BAT 240
Working Directory: C:\BTT522
     Shortcut Key: none
 
------------------------------------------------------------------------------
 
 

Typing emurst -help or emurst -p without a number causes a segmentation
fault.

None.

Running emurst with no power to the target board causes a crash.

Make sure target board is powered up before running emurst.

The -p parameter is read as hexadecimal, and translated into decimal
when referring to the destination driver.
 
i.e. emurst -p b would attempt to access /dev/sd11
 and emurst -p 11 would attempt to access /dev/sd17

Use hexadecimal to represent the decimal port number.

HEX CONVERTER DEFECTS

The hex utility output files contain address discontinuities
with some address ranges not being displayed.

None.

LINKER DEFECTS

Using the -s switch for the linker generates many relocation
symbol errors when linking relocateable object modules which
have not had symbols stripped.

Do not strip symbols in the final linker step when the
error occurs.  The resulting object module will be larger
but execution behavior should not change.

The address of two different locations in memory is assembled
by mpasm to the same address.  The problem occurs with both PC
and workstation tools.

none

PDM DEFECTS

    The dlog command does not work as is explained in the UG.
 
    From a PDM command window if you type dlog filename, whatever commands
    you type in the PDM command window should get logged in the file named
    filename.  However, it looks like the entire screen is being logged,
    not just the commands.
 
    For example:
 
    From a PDM command window:
 
    PDM:1>> dlog init.pdm
    PDM:2>> spawn mpsim
    PDM:3>> send -g MP load sample
    PDM:4>> dlog close
 
    The file init.pdm is supposed to have:
 
    spawn mpsim
    send -g MP load sample
 
    However, init.pdm actually contains
 
    PDM:2> spawn mpsim
    PDM:3> send -g MP load sample
    PDM:4> dlog close

None.

Sometimes using the prun -r command from the PDM causes the debuggers to
crash.

Instead of using "prun -r", type "send -r run" from the PDM command line.
Remember though that "send -r run" does not perform the debugger synch-
ronization.

When running pdm from a shell script or any other kind of parent program,
pdm terminates the parent process when pdm exits.

None.

RTS DEFECTS

The system() function defined in stdlib.h is not supported
for the mvp.  Using this function results in linker errors
since system() is not defined in the run time system libraries.
The system() function should have a dummy body supplied and
unsupported functions in standard header files documented.

Do not use the system() function or supply a body for
it.

Autoinitialization of data within a single .bss area
is not initialized correctly.  Values are assumed to be
aligned on the correct byte within a 4 byte initialization
record (.cinit).  Multiple initializations are actually
leftmost adjusted within a word.  Multiple values
initialized within the same word may overlay each other
and/or be placed at a wrong location within the correct
word.
 

none