Slide 14 of 97
Notes:
In our example we have used the LDH or LoadHalf Word instruction. However, the C6x architecture is a native 32-bit machine, and is also byte addressable. There are three different load instructions available on the C6x, the LDW or Load Word, the LDH or Load Half Word, and the LDB or Load Byte instruction.
We can also allow for either signed loads or unsigned loads with slight modification to the instruction syntax. We're loading data and in a two's complement number system, so the leading bit or the most significant bit also contains sign information. For a negative number, that sign bit is one. In order to bring it into a register that's 32 bits, we must be able to sign extend to indicate a negative value.
The CPU also supports three store instructions and they are STW, or store word, for 32-bit values, store H for 16-bit values, and store byte for 8-bit values.
