Case Study #1

• 80 MIPS LC549

  • 32K words of RAM, 16K words of ROM
  • 3 serial ports, host port interface

• (80 MIPS) x (.6 mA/MIPS) x 3.0V =

108 mW

• IDLE 1, 2, 3 modes ; PLL options

• Size: micro*BGA = 12 x 12 x 1.4 mm

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For case study #1, the straightforward answer is the C54x. The device choice would need to include the integration of both memory and peripherals on-chip. This is based on the requirement to minimize the power (off-chip accesses increase power dissipation) and minimize space (off-chip memories require large system space). While a large ROM device may be best suited for this application, the LC549 also provides large memory and peripheral integration. The LC549 utilizes 32K words of RAM and 16K words of ROM, one time-division multiplexed serial port, two buffered serial ports, and a host port interface. An 80 MIPS device operating at 3.0V would dissipate just over 140 mW using on-chip resources (assumes 0.6 mA/MIPS). This mA/MIPS number will move to .45 mA/MIPS in the next process technology node. The LC548 and LC549 have three power down modes (IDLE1, IDLE2, IDLE3). IDLE1 dissipates 31.2 mW (@ 80 MIPS), IDLE2 dissipates 9.6 mW), and IDLE3 dissipates 1.65 mW. These numbers assume that the PLL is enabled. If the PLL is enabled there are 31 different options to multiply the external clock (e.g. a x4 PLL would allow a 20 Mhz external clock to drive 80 Mhz, and hence 80 MIPS, on-chip. The small size of the LC549 BGA package (12x12x1.4) enables small system size.